1. Field of the Invention
The present invention relates to a pipelined analog to digital converter, especially to a pipelined analog to digital converter with a capacitor augmented and randomly selected as a feedback capacitor to compensate capacitance mismatch.
2. Related Art of the Invention
Analog-to-digital conversion processes to convert an analog signal, which is most commonly represented as a voltage, into a digital format. Serial, delta-sigma, parallel, and pipelined methods are well known analog-to-digital conversion architectures. Different architectures are suited to different needs.
A serial analog-to-digital architecture offers a wide range of performance in analog-to-digital conversion, from low power and low resolution to quantizations with very high resolutions. A serial architecture typically quantizes analog data at the rate of one bit per cycle. Therefore, a digital sample having N bits of resolution will take N cycles to complete quantization.
A delta-sigma analog-to-digital architecture is often used in audio signal processing. The architecture is designed to translate high-speed, low-resolution samples into higher-resolution, lower-speed outputs. This process is also referred to as oversampling because more samples of the analog data are quantized than actually outputted.
By contrast, a parallel analog-to-digital architecture provides the fastest quantization rate per analog signal. In a parallel (or “flash”) architecture, a digital value per cycle is produced for each analog data sample, without regard to N, the number of bits of resolution. A parallel architecture requires that all quantization levels be simultaneously compared to the analog signal. This results in the use of 2N−1 comparators and 2N+1 resistors to achieve a digital value, with N bits of resolution, per cycle. For higher resolution, the circuit complexity of the flash analog-to-digital converter (“ADC”) will greatly increase.
Two-step flash architectures arose to address the circuit complexity issue of flash ADCs, where the two-step flash ADCs first performs a coarse quantization, the held signal is then subtracted from an analog version of the coarse quantization, and the residue is then more finely quantized. This significantly reduces the number of comparators required in a standard flash ADC architecture, but additional clock cycles are required to process the signal due to the extra stage. Another enhancement arose, where interstage gain was used to tolerate larger comparator offset for second stage comparators, which ultimately led to the pipelined ADC architecture employing multiple stages. The sampled input at each stage of a pipelined ADC architecture is converted to a particular resolution of the stage, such as n bits per stage.
Pipelined analog-to-digital architecture, like serial analog-to-digital architecture, is a method of quantizing an analog signal in stages. Algorithms exist for obtaining either 1 or 1.5 bits of resolution per stage. In a 1.5-bit per stage converter, the digital output Di of each stage is either 1, 0, or −1. In a 1-bit per stage converter, the digital output of each stage is either 1 or −1 (or 1 or 0). For either algorithm, N stages are used for an N-bit digital value. One bit is resolved at each stage with the result and a residual analog signal sample passed along to the next stage for resolution of another bit.
In a 1.5-bit per stage converter, the other ½ bit in each stage is redundant. Digital correction logic eliminates the redundancy to produce an N-bit result. Producing a single digital value for a single analog input requires N cycles, one for each stage. However, the pipelining permits a high degree of parallelism, so that one output per cycle can be produced after the pipeline fills up.
In prior art ADC circuits such as a 1.5-bit ADC, charge transfer occurs from one input capacitor to a second capacitor in the feedback loop of an amplifier via the virtual ground node of the amplifier. In this manner, the input capacitor discharges to the feedback capacitor, giving rise to an output voltage that is proportional to the capacitor ratio (i.e., input capacitance/feedback capacitance). For example, a gain of “2” may be created by providing an input capacitor having a capacitance value twice that of the feedback capacitor.
FIG. 1 shows a schematic diagram of a conventional pipelined 1.5-bit ADC 10, where the ADC 10 has, for example, a 12-bit output (N=12). The ADC 10 comprises a plurality of 1.5-bit sub converter stages 101–110 and a final flash stage 112. The input analog voltage signal is resolved into a 1.5-bit digital code in a coarse analog-to-digital sub-converter (ADSC) within the first stage 101. With a 1.5-bit ADC, only three codes are possible, such as 00, 01, and 10. The resulting 1.5-bit code is outputted to a digital error correction (DEC) circuit 120. The code is also converted, via a digital-to-analog sub-converter (DASC) within the first stage 101, back into a coarse analog signal with one of three predetermined analog values, such as −Vref, 0, +Vref. The result is subtracted from the sampled-and-held analog input signal Vin via a subtractor within the first stage 101. The resulting analog “residue” is gained up by a factor of two using a multiplier to become the input voltage for the successive conversion, which is sent to the next stage 102. The output sub-words from the 1.5-bit stages 101–110 are processed by the DEC circuit 120 for correcting the associated comparator and amplifier offset due to the coarse treatment in each 1.5-bit stage. The corrected result is then concatenated with the output of the final flash stage 112 to obtain a 12-bit digital counterpart of the input signal;
FIG. 2A shows a circuit diagram to fulfill one 1.5-bit stage in a sampling phase, the 1.5-bit stage such as the stage 101 shown in FIG. 1 comprises an amplifier 140, two capacitors C1 and C2 connected in parallel between an input node 142 and an inverting input of the amplifier 140, a non-inverting input of the amplifier 140 is connected to ground. The input analog voltage Vin is further fed to two comparators 152 and 154 to compare with two reference voltages, respectively. The comparison results of the two comparators 152 and 154 are sent to a digital output unit 150 for generating a digital output Di for this stage. The two reference voltages are, for example, +Vref/4 and −Vref/4 and used to quantize the input voltage into the digital output Di (1, 0, or −1) of each stage, as shown in FIG. 3. During the sampling phase, the input voltage Vin is established across the capacitors C1 and C2.
FIG. 2B shows a circuit diagram to fulfill one 1.5-bit stage in a hold (amplifying) phase. In this phase, switches (not shown) are used to connect one node of the capacitor C1, which is originally connected to the input node, to the output node of the amplifier 140. The switches further connect one node of the capacitor C2, which is originally connected to the input node, to Di·Vref, which is the product of the digital output Di and the reference voltage Vref. Therefore, residual voltage can be generated at output node of the amplifier 140 in the amplifying phase.
In the above-mentioned pipelined ADC, the mismatch of capacitor will cause significant error. Therefore, various approaches are proposed to compensate the capacitor mismatch or minimize the effect of capacitor mismatch.
U.S. Pat. No. 6,420,991 discloses a dynamic element matching for converting element mismatch into white noise for a pipelined ADC. In a sample period, as shown in FIG. 5 of that patent, all capacitors are connected in parallel between the input node and the inverting input of an amplifier, which is virtually grounded through the non-inverting input of the amplifier. In a hold (amplifying) period, the connection of the input connection capacitors are fixed once the digital codes from the sub-converter are determined. In addition, the feedback capacitor is usually predetermined to be C11 for all times. The other capacitors C21–C2p are randomly connected to Vref, GND and −Vref with a pseudo-random code generated by a digital circuit. However, this patent does not disclose any way to randomly use capacitors and much improvement is desired.